아트메가 BLDC 테스트 예제

#define F_CPU 16000000UL  // 16 MHz
 
#include<avr/io.h>
#include<util/delay.h>
#include <avr/interrupt.h>
 
void _init_port();
void _init_timer();
void _init_interrupt();
void _init_uart();
void _init_i2c();
void _init_spi();
 
 
unsigned char count        = 0;
unsigned int  stage        = 0;
int main(void)
{
 
    _init_port();
    DDRA     = 0xFF;    // MEMORY
    PORTA     = 0x00;
    _init_timer();
    _init_interrupt();
//    _init_uart();
//    _init_i2c();
//    _init_spi();
    sei();
    unsigned short phase[360];
    for (int i=0; i<360; i++)
    {
        phase[i] = (sin((float)i*0.017)+1.0)*32767;
    }
 
 
    while(1)
    {
    for( int i=0; i<360; i++)
    {
        OCR1AH = phase[(i+0)%360] >>8;
        OCR1AL = phase[(i+0)%360] & 0xFF;
        
        OCR1BH = phase[(i+120)%360] >>8;
        OCR1BL = phase[(i+120)%360] & 0xFF;
        
        OCR1CH = phase[(i+240)%360] >>8;
        OCR1CL = phase[(i+240)%360] & 0xFF;
 
        _delay_ms(10);
 
    }
    PORTA = !PINA;
    }
 
    return 0;
 
}
 
void _init_port()
{
//    DDRA     = 0xFF;    // MEMORY
//    PORTA     = 0x00;
/*
    DDRB     = 0x00;    // SPI, TIMER 0~2
    PORTB     = 0x00;
    DDRC     = 0x00;    // MEMORY
    PORTC     = 0x00;
    DDRD     = 0x00;    // EXT.INT/CLOCK
    PORTD     = 0x00;
    DDRE     = 0x00;    // UART, EXT.INT TIMER 3
    PORTE     = 0x00;
    DDRF     = 0x00;    // ADC . JTAG
    PORTF     = 0x00;
*/
 
 
}
 
void _init_timer()
{
    DDRB     = 0b11111111;
    PORTB    = 0b00000000;
/*
    TIMSK    |= (1<< TOIE0)     | (1<< OCIE0);          //INTERRUPT ENABLE
    TCCR0     |= (1 <<WGM21 ) | (1 <<WGM20);            //PWM
    TCCR0     |= (1 <<COM21 ) | (1 <<COM20);            // OC2PIN SET
    TCCR0     |= (0 <<CS22)     | (1<<CS21) | (1<<CS20);//CPU 클락
    TIFR    |= (0 <<OCF0)     | (0 <<TOV0);
*/
 
 
 
 
/* COM X1/0 At FAST PWM
    00 : disconnect(GPIO)
    01 : toggle on compare match // only OCnA
    10 : clear on compare match set on bottom
    11 : set on compare match clear on bottom
*/
/* CSn 2/1/0 
    000 : stop
    001 : /1
    010 : /8
    011 : /64
    100 : /256
    101 : /1024
    110 : /ext at falling edge
    111 : /ext at rising edge
*/
    TCCR1A    |= (1 <<COM1A1 )    | (0 <<COM1A0 );
    TCCR1A    |= (1 <<COM1B1 )    | (0 <<COM1B0 );
    TCCR1A    |= (1 <<COM1C1 )    | (0 <<COM1C0 );
//    TCCR1B    |= (0 <<ICNC1)    | (0 <<ICES1);
 
    TCCR1B    |= (1 <<WGM13)    | (1 <<WGM12);
    TCCR1A    |= (1 <<WGM11 )    | (0 <<WGM10);
 
    TCCR1B    |= (0 <<CS12)    | (0 <<CS11)    | (0 <<CS10);
 
    TCNT1H = 0x00;
    TCNT1L = 0x00;
    
    OCR1AH = 0x00;
    OCR1AL = 0x00;
    OCR1BH = 0x00;
    OCR1BL = 0x00;
    OCR1CH = 0x00;
    OCR1CL = 0x00;
    
    ICR1H = 0xFF;
    ICR1L = 0xFF;
    
//    TIMSK |= (1 <<OCIE1A)    | (1 <<OCIE1B);
//    ETIMSK |= (1 <<OCIE1C);
//    TIMSK |= (1 <<TICIE1)    | (1 <<TOIE1);
 
//    TIFR |= (1 <<OCF1A)    | (1 <<OCF1B);
//    ETIFR |= (1 <<OCF1C);
//    TIFR |= (1 <<ICF1)    | (1 <<TOV1);
 
/*
    TIMSK    |= (1<< TOIE2)     | (1<< OCIE2);          //INTERRUPT ENABLE
    TCCR2     |= (1 <<WGM21 ) | (1 <<WGM20);            //PWM
    TCCR2     |= (1 <<COM21 ) | (1 <<COM20);            // OC2PIN SET
    TCCR2     |= (0 <<CS22)     | (1<<CS21)     | (1<<CS20); //CPU 클락
*/
    
}
 
void _init_interrupt()
{
    DDRD    = 0x00;
    PORTD    = 0xFF;
    EICRA    |= ( 1 <<ISC11)    | ( 0 <<ISC10)    | ( 1 <<ISC01)    | ( 0 <<ISC00);
    EIMSK    |= ( 1 <<INT1)    | ( 1 <<INT0);
    EIFR    |= ( 1 <<INTF1)    | ( 1 < INTF0);
}
 
void _init_uart()
{
}
 
void _init_i2c()
{
}
 
void _init_spi()
{
}
/*
ISR( TIMER2_COMP_vect )
{
    PORTA = 0xFF;
}



ISR( TIMER2_OVF_vect )
{
    PORTA = 0x00;

}
*/
 
 
ISR( INT0_vect )
{
 
    PORTA = 0x00;
    _delay_ms(100);
}
 
ISR( INT1_vect )
{
    PORTA = 0xFF;
}