ATMEGA128 스펙 study

atmega128 pro.pdf

ATMEGA128.pdf

http://cyhome.cyworld.com/?home_id=a0132324&postSeq=6358096

http://blog.naver.com/s_paper/220119097404

http://blog.naver.com/jbivanlee/40121783475

아트메가128의 특징

• Harvard architecture

• 8비트 고성능-저전력 마이크로프로세서(고성능???)

• RISC 아키텍쳐(133개의 명령어, 대부분이 1사이클에 실행 가능(곱셈은 2사이클)

• 32*8 범용 레지스터

• 128KB Flash(10M Write/Erase cycle), 4KB EEPROM(100M Write/Erase cycle) 4KB SRAM

• 64KB까지 외부 메모리 확장 가능(Up to 64Kbytes Optional External Memory Space)

• JTAG (IEEE std. 1149.1 Compliant) Interface

• Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

• Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and Capture

Mode

• Two 8-bit PWM Channels

• 6 PWM Channels with Programmable Resolution from 2 to 16 Bits

• Output Compare Modulator

• 8-channel, 10-bit ADC

• Byte-oriented Two-wire Serial Interface

• Dual Programmable Serial USARTs

• Master/Slave SPI Serial Interface

• Power-on Reset and Programmable Brown-out Detection

• External and Internal Interrupt Sources

• Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and

Extended Standby (뒷부분에 추가 설명)

• Operating Voltages

– 4.5 - 5.5V ATmega128

아트메가의 (특수한)모드

 The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions

until the next interrupt or Hardware Reset.

 In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping.

The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions.

 In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption.

 In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.

아트메가 핀의 사용과 종류

Port A (PA7..PA0) 

 Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port A output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,

even if the clock is not running. Port A also serves the functions of various special features of the ATmega128 as listed on page 72.(외부 메모리 인터페이스로 활용 가능)

Port B (PB7..PB0)

 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running. Port B also serves the functions of various special features of the ATmega128 as listed on page 73.( Counter 0/1/2의 PWM 출력, SPI 통신포트로 사용 가능)

Port C (PC7..PC0)

 Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the Atmel® AVR®ATmega128 as listed on page 76. In ATmega103 compatibility mode, Port C is output only, and the port C pins are not tristated when a reset condition becomes active.

(외부 메모리 인터페이스로 활용 가능)

Note: The ATmega128 is by default shipped in ATmega103 compatibility mode. Thus, if the parts are not

programmed before they are put on the PCB, PORTC will be output during first power up, and until

the ATmega103 compatibility mode is disabled.

Port D (PD7..PD0) 

 Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega128 as listed on page 77. (외부 인터럽트, 외부 클럭/타이머 input으로 활용 가능)

Port E (PE7..PE0) 

 Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,even if the clock is not running. Port E also serves the functions of various special features of the ATmega128 as listed on page 80. 

(외부 인터럽트, 외부 클럭/타이머 input counter3 output, Analog comperator, Programming in/out, UART0로 활용 가능)

Port F (PF7..PF0)

 Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs. The TDO pin is tri-stated unless TAP states that shift out data are entered. Port F also serves the functions of the JTAG interface.

 In ATmega103 compatibility mode, Port F is an input Port only.

Port G (PG4..PG0)

 Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features. The port G pins are tri-stated when a reset condition becomes active, even if the clock is not running.

In ATmega103 compatibility mode, these pins only serves as strobes signals to the external

memory as well as input to the 32kHz Oscillator, and the pins are initialized to PG0 = 1, PG1 = 1,

and PG2 = 0 asynchronously when a reset condition becomes active, even if the clock is not

running. PG3 and PG4 are oscillator pins.

AVCC

 AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected

to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 

AREF

 AREF is the analog reference pin for the A/D Converter.

PEN

 PEN is a programming enable pin for the SPI Serial Programming mode, and is internally pulled high . By holding this pin low during a Power-on Reset, the device will enter the SPI Serial Programming mode. PEN has no function during normal operation.

CPU 설명

- 8비트 버스에 주변기기가 물려있음

- 32*8 범용레지스터

- 6*32 간접 주소 포인터 레지스터

레지스터 정리

Status Register

< 명령 수행 후에 그 결과의 특성을 기록하는 상태 레지스터, 인터럽트 진입시에 백업되거나, 복원되지 않는다.>

 The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.

The AVR status Register – SREG – is defined as:

• Bit 7 – I: Global Interrupt Enable

 The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared in software with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination

for the operated bit. A bit from a register in the Register file can be copied into T by the

BST instruction, and a bit in T can be copied into a bit in a register in the Register file by the BLD

instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a half carry in some arithmetic operations. Half carry is useful in

BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow

flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the

“Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the

“Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction

Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

Watchdog Timer 

The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1MHz. This is

the typical value at VCC = 5V. See characterization data for typical values at other VCC levels. By

controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as

shown in Table 22 on page 56. The WDR – Watchdog Reset – instruction resets the Watchdog

Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.

Eight different clock cycle periods can be selected to determine the reset period. If the reset

period expires without another Watchdog Reset, the ATmega128 resets and executes from the

Reset Vector. For timing details on the Watchdog Reset, refer to page 53.

To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, 3

different safety levels are selected by the Fuses M103C and WDTON as shown in Table 21.

Safety level 0 corresponds to the setting in ATmega103. There is no restriction on enabling the

WDT in any of the safety levels. Refer to “Timed Sequences for Changing the Configuration of

the Watchdog Timer” on page 57 for details.

TCNT : 카운터

TCCR : 모드 설정

OCR : 비교점 설정

TIMSK : 인터럽트 설정

<Example Code>

void _init_timer()

{

DDRB = 0b10000000;

TIMSK |= (1<< TOIE2) | (1<< OCIE2);   //INTERRUPT ENABLE

TCCR2 |= (1 <<WGM21 ) | (1 <<WGM20); //PWM

TCCR2 |= (1 <<COM21 ) | (1 <<COM20); // OC2PIN SET

TCCR2 |= (1 <<CS22) | (0<<CS21) | (1<<CS20); //CPU 클락

}

ISR( TIMER2_COMP_vect )

{

PORTA = 0xFF;

}

ISR( TIMER2_OVF_vect )

{

PORTA = 0x00;

}

// 타이머0 오버플로우 인터럽트
    TCCR0=4; TCNT0=6;   TIMSK=1;  //16000000/  64/250=1000Hz=1ms,  (256-250)=6
    TCCR0=5; TCNT0=131; TIMSK=1;  //16000000/ 128/125=1000Hz=1ms,  (256-125)=131
    TCCR0=5; TCNT0=6;   TIMSK=1;  //16000000/ 128/250= 500Hz=2ms,  (256-250)=6
    TCCR0=6; TCNT0=6;   TIMSK=1;  //16000000/ 256/250= 250Hz=4ms,  (256-250)=6
    TCCR0=7; TCNT0=6;   TIMSK=1;  //16000000/1024/250=62.5Hz=16ms, (256-250)=6

// 타이머0 매치 인터럽트
    TCCR0=0x0B; OCR0= 49;  TIMSK=2;  //16000000/  32/(1+ 49)=10000Hz=100us
    TCCR0=0x0C; OCR0=249;  TIMSK=2;  //16000000/  64/(1+249)= 1000Hz=1ms
    TCCR0=0x0D; OCR0=124;  TIMSK=2;  //16000000/ 128/(1+124)= 1000Hz=1ms
    TCCR0=0x0D; OCR0=249;  TIMSK=2;  //16000000/ 128/(1+249)=  500Hz=2ms
    TCCR0=0x0E; OCR0=249;  TIMSK=2;  //16000000/ 256/(1+249)=  250Hz=4ms
    TCCR0=0x0F; OCR0=155;  TIMSK=2;  //16000000/1024/(1+155)= 100.16..Hz=9.984ms
    TCCR0=0x0F; OCR0=249;  TIMSK=2;  //16000000/1024/(1+249)= 62.5Hz=16ms

// 타이머1 오버플로우 인터럽트
    TCCR1B=1; TCNT1=49536; TIMSK=4; //16000000/  1/16000=1000Hz=1ms,  (65536-16000)=49536
    TCCR1B=1; TCNT1=33536; TIMSK=4; //16000000/  1/32000= 500Hz=2ms,  (65536-32000)=33536
    TCCR1B=2; TCNT1=63536; TIMSK=4; //16000000/  8/ 2000=1000Hz=1ms,  (65536- 2000)=63536
    TCCR1B=2; TCNT1=61536; TIMSK=4; //16000000/  8/ 4000= 500Hz=2ms,  (65536- 4000)=61536
    TCCR1B=2; TCNT1=45536; TIMSK=4; //16000000/  8/10000= 200Hz=5ms,  (65536-10000)=45536
    TCCR1B=2; TCNT1=35536; TIMSK=4; //16000000/  8/20000= 100Hz=10ms, (65536-20000)=35536
    TCCR1B=4; TCNT1=59286; TIMSK=4; //16000000/256/ 6250=  10Hz=100ms,(65536- 6250)=59286
    TCCR1B=4; TCNT1= 3036; TIMSK=4; //16000000/256/62500=   1Hz=1sec, (65536-62500)= 3036

// 타이머1 A매치 인터럽트
    TCCR1B=0x09; OCR1A=1474;  TIMSK=0x10; //14745600/  1/(1+ 1474)=9997.01695Hz=100.02984us
    TCCR1B=0x09; OCR1A=1599;  TIMSK=0x10; //16000000/  1/(1+ 1999)=10KHz=100us
    TCCR1B=0x09; OCR1A=15999; TIMSK=0x10; //16000000/  1/(1+15999)=1000Hz=1ms
    TCCR1B=0x09; OCR1A=31999; TIMSK=0x10; //16000000/  1/(1+31999)= 500Hz=2ms
    TCCR1B=0x0A; OCR1A= 1999; TIMSK=0x10; //16000000/  8/(1+ 1999)=1000Hz=1ms
    TCCR1B=0x0A; OCR1A= 3999; TIMSK=0x10; //16000000/  8/(1+ 3999)= 500Hz=2ms
    TCCR1B=0x0A; OCR1A= 9999; TIMSK=0x10; //16000000/  8/(1+ 9999)= 200Hz=5ms
    TCCR1B=0x0A; OCR1A=19999; TIMSK=0x10; //16000000/  8/(1+19999)= 100Hz=10ms
    TCCR1B=0x0C; OCR1A= 6249; TIMSK=0x10; //16000000/256/(1+ 6249)=  10Hz=100ms
    TCCR1B=0x0C; OCR1A=31249; TIMSK=0x10; //16000000/256/(1+31249)=   2Hz=500ms
    TCCR1B=0x0C; OCR1A=62499; TIMSK=0x10; //16000000/256/(1+62499)=1Hz=1sec

// 타이머2 매치 인터럽트
    TCCR2=0x0B; OCR2=249;  TIMSK=0x80;  //16000000/  64/(1+249)=1000Hz=1ms

adc

http://miobot.tistory.com/28